1. Field of the Invention
The present invention relates to switch circuits, and, in particular, to switch circuits for track-and-hold amplifiers for use in applications like high-speed analog-to-digital converters.
2. Description of the Related Art
High-speed analog-to-digital (A/D) converters are important hardware components in many digital signal processing applications. As the performance requirements of mixed-signal and communications systems continue to increase, subsystems such as A/D converters are required to meet higher sampling frequencies and resolutions. At the same time, there is increasing pressure to reduce the power supply voltage. Some A/D converters have a track-and-hold amplifier (TH amp) at the front end and a quantizer at the back end. The performance of such A/D converters is often limited by the performance of the TH amp.
FIG. 1 shows a block diagram of a generalized open-loop track-and-hold amplifier 100 typically used in applications such as A/D converters. Although one of the characteristics of a closed-loop TH amp architecture is high-accuracy, the frequency response limitation of such an approach is typically a dominant design tradeoff. As a result, the open-loop TH amp architecture of FIG. 1 is often employed for high-frequency applications. TH amp 100 has input buffer 102 followed by switch 104, hold capacitors 106, and output buffer 108. Input buffer 102 provides isolation between switch 104 and the differential analog inputs (V.sub.11 and V.sub.12). Output buffer 108 is intended to drive the input of another component (e.g., the quantizer of an A/D converter), where the other component is on the same integrated circuit as TH amp 100.
In operation, the state of switch 104 (i.e., either open or closed) is controlled by two control signals: the track control signal V.sub.TK and the hold control signal V.sub.HD. When (V.sub.TK &gt;V.sub.HD), switch 104 is closed and voltages corresponding to the differential analog inputs (V.sub.11 and V.sub.12) are accumulated in hold capacitors 106. When (V.sub.HD &gt;V.sub.TK), switch 104 is open and the voltages accumulated in hold capacitors 106 are available to be transmitted by output buffer 108 as the output of TH amp 100.
One possible implementation of a track-and-hold circuit is described in P. Vorenkamp and J. P. M. Verdaasdonk, "Fully Bipolar, 120-Msample/s 10-b Track-and-Hold Circuit," IEEE Journal of Solid-State Circuits, vol. 27, no. 7, pp. 988-992, July 1992 ("the Vorenkamp reference"), the teachings of which are incorporated herein by reference. In that implementation, the input buffer is a common emitter differential amplifier with a linearization diode in series with each collector. One disadvantage of this approach is that the d-c bias voltage from the series diodes limits power supply reduction. For high-speed systems with relatively low resolution, the diodes can be omitted. However, to prevent serious degradation of linearity, a relatively high bias current in the differential amplifier is required, as described in B. Pregardier, et al., "A 1 Gsample/s 8b Silicon Bipolar Track&Hold IC," IEEE International Solid-State Circuits Conference, San Francisco, Calif., February 1995, the teachings of which are incorporated herein by reference.
Another possible implementation of a track-and-hold circuit is described in R. Jewett, et al., "A 12b 20MS/s Ripple-through ADC," IEEE International Solid-State Circuits Conference, San Francisco, February 1992, the teachings of which are incorporated herein by reference. In that implementation, an A/D converter employs an amplifier with a gain of two that requires two diodes in series with each collector. In this case, power supply reduction is even further limited.
FIG. 2 shows a circuit diagram of a basic input buffer design that could be used for input buffer 102 of TH amp 100 of FIG. 1. Input buffer 102 is essentially a differential amplifier formed by two transistor devices (Q.sub.1 and Q.sub.2). The emitters of devices Q.sub.1 and Q.sub.2 are each biased with a current source I.sub.B1. The dynamic range of the differential amplifier is extended by the emitter resistor 2R.sub.1. When a differential input (V.sub.11 and V.sub.12) is applied, the collector current of each device has a nonlinearity that is encoded by the base-emitter junctions with the series emitter resistance 2R.sub.1. The collectors of devices Q.sub.1 and Q.sub.2 are each loaded with a series connection of a resistor R.sub.1 and a diode-connected device (Q.sub.3, Q.sub.4). Thus, the collector current nonlinearity is decoded resulting in an essentially linear transfer characteristic.
FIG. 3 shows the transfer characteristic of the buffer circuit of FIG. 2 with the output analyzed as the sum of two contributions. The first contribution is the differential voltage from the resistor loads (V.sub.R). The second contribution is the differential voltage from the diode loads (V.sub.D). Thus, the total output is V.sub.OUT =V.sub.R +V.sub.D.
FIG. 4 shows the integral nonlinearity (INL) as a fraction of the full-scale (FS) output for the buffer circuit of FIG. 2. Notice that INL(V.sub.OUT)=INL(V.sub.R)+INL(V.sub.D) is approximately zero. Without the linearization diodes, the simulated total harmonic distortion (THD) is less than -50 dB.
FIG. 5 shows a circuit diagram of a basic design that could be used in implementing TH amp 100 of FIG. 1. In such an implementation, the circuit of FIG. 5 corresponds to half of switch 104, one hold capacitor 106, and half of output buffer 108 of TH amp 100, as depicted in FIG. 1. Devices Q.sub.1 and Q.sub.2 are used to steer current to the emitter follower Q.sub.3. When (V.sub.TK &gt;V.sub.HD), the switch is in the track mode (i.e., closed) as the bias current I.sub.B1 is steered to device Q.sub.3. When (V.sub.TK &lt;V.sub.HD), the switch is in the hold mode (i.e., open) as the current is steered towards bias voltage V.sub.CC via the load resistor R.sub.1 in the input buffer stage of FIG. 2 preceding the switch. The emitter-follower-based switch directly drives the hold capacitor (e.g., C.sub.H .about.2.5 pF). The hold capacitor output then drives the emitter follower output buffer Q.sub.4.
When TH amp 100 of FIG. 1 is in the hold mode with a nonzero input, there is feedthrough to the hold capacitor output due to imperfections in the switch, such as finite junction capacitance. This feedthrough can interfere with the operation of a high-resolution A/D converter driven by TH amp 100.